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user:tmeissner

T. Meissner (tmeissner)

First Name Torsten
Last Name Meissner
Email
SkypeID
GoogleID TorstenMeißner
Department
Organization
Location Dresden
Country Germany
Website
Github https://github.com/tmeissner
Status

I'm an FPGA-Engineer doing design and verification using VHDL, SystemVerilog and PSL for high security hardware.

Interests

  • Functional coverage, Constrained random
  • Assertion based design & verification (PSL, SVA)
  • Formal verification
  • Scripting, design automation

Proposals

user/tmeissner.txt · Last modified: 07.10.2016 12:08 by tmeissner