# VHDL CoreLib

### Notes

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proposals:tbv:tbv12

# TBV12 - Sparse arrays

 Summary Sparse arrays Proposal submitted mm/dd/yy

### Enhancement

Associative arrays could be used to model sparse arrays. However, sparse arrays are more specific. They are used specifically for modeling large memories efficiently when only a small percentage of the memory addresses are used in any given simulation.

BTW, it would also be good to define load and dump operations for associative/sparse arrays.