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proposals:synth:components
Author Patrick Lehmann
Last Update 13.09.2016
Related Proposals

Synthesizable Functions

Many basic gates can be expressed as functions. This packages extends VHDLs operators for std_logic and similar types to represent common logic gates as a function of N inputs and one output signal.

More over, the syntax a ⇐ b when rising_edge(Clock) offers many new ways to describe synchronous hardware. Functions can be used instead of b to implement more complex clocked hardware then simple D-flip-flops. The packages also provides common flip-flops, counters and shift-registers, which can be described as a one-liner.

package components is
  -- implement an optional register stage
  function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean;
 
  -- FlipFlop functions
  -- ===========================================================================
  -- RS-FlipFlops
  function ffrs(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic;        -- RS-FlipFlop with dominant rst
  function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic;        -- RS-FlipFlop with dominant set
  -- D-FlipFlops (Delay)
  function ffdre(q : std_logic;        d : std_logic;        rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0')                        return std_logic;         -- D-FlipFlop with reset and enable
  function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (7 downto 0 => '0')) return std_logic_vector;  -- D-FlipFlop with reset and enable
  function ffdse(q : std_logic;        d : std_logic;        set : std_logic := '0'; en : std_logic := '1')                                                          return std_logic;         -- D-FlipFlop with set and enable
  -- T-FlipFlops (Toggle)
  function fftre(q : std_logic;        t : std_logic;        rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0')                        return std_logic;         -- T-FlipFlop with reset and enable
  function fftse(q : std_logic;        t : std_logic;        set : std_logic := '0'; en : std_logic := '1')                                                          return std_logic;         -- T-FlipFlop with set and enable
 
  -- counter
  function upcounter_next(cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned;
  function upcounter_equal(cnt : unsigned; value : natural) return std_logic;
  function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed;
  function downcounter_equal(cnt : signed; value : integer) return std_logic;
  function downcounter_neg(cnt : signed) return std_logic;
 
  -- shiftregisters
  function shreg_left(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector;
  function shreg_right(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector;
  -- rotate registers
  function rreg_left(q : std_logic_vector; en : std_logic := '1') return std_logic_vector;
  function rreg_right(q : std_logic_vector; en : std_logic := '1') return std_logic_vector;
 
  -- compare
  function comp(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector;
  function comp(value1 : unsigned; value2 : unsigned) return unsigned;
  function comp(value1 : signed; value2 : signed) return signed;
  function comp_allzero(value : std_logic_vector) return std_logic;
  function comp_allzero(value : unsigned)         return std_logic;
  function comp_allzero(value : signed)           return std_logic;
  function comp_allone(value  : std_logic_vector) return std_logic;
  function comp_allone(value  : unsigned)         return std_logic;
  function comp_allone(value  : signed)           return std_logic;
 
  -- multiplexing
  function mux(sel : std_logic; sl0  : std_logic;        sl1  : std_logic)        return std_logic;
  function mux(sel : std_logic; slv0 : std_logic_vector; slv1 : std_logic_vector) return std_logic_vector;
  function mux(sel : std_logic; us0  : unsigned;         us1  : unsigned)         return unsigned;
  function mux(sel : std_logic; s0   : signed;           s1   : signed)           return signed;
end package;

Source: PoC.components

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proposals/synth/components.txt · Last modified: 14.09.2016 01:36 by paebbels