Transferred from IEEE P1076 WG Collected Requirements list: FunctionalCoverage

Requirements from past IEEE and Accellera VHDL lists:

Conditional coverage collection
Separate coverage goals for each bin

Coverage is a data structure. As such it can be implemented in a protected type. The Open Source VHDL Verification Methodology (OSVVM) project has implemented such a package and would be a suitable alternative to adding syntax to the language.

Available now. No cost for vendors to implement. Updateable frequently.

While SystemVerilog and 'e' implement FC as a declarative object, constructing the model and collecting coverage sequentially has some distinct advantages. The coverage model does not need to be captured in a single declaration, but rather can be captured incrementally when the precision and/or fidelity of the model demands it. Any sequential construct may be used to construct model or capture coverage.

One unique capability the OSVVM package offers is the integration of functional coverage and randomization. With only constrained random capability, generating N stimulus items takes O(n * log n). By randomly selecting a coverage hole, and passing that to the stimulus generation process, under good conditions, run times can be reduced to O(n).

The OSVVM packages are available here.
Latest packages: github.com/JimLewis/OSVVM

With the current language definition, there are some things that the package based approach cannot do or would be clumbsey to do. There are a number of enhancements that we can make to protected types, subprogram interfaces, and subprograms that would expand the capabilities of the package based approach. Most/all of these are inspired by features that are already in ADA.

How do we better leverage PSL - particularly for transition based constraints.

See the documentation that accompanies the open-source packages.

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