VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn’t replace but rather complements traditional testing methodologies by supporting a “test early and often” approach through automation.

NOTE: SystemVerilog support is experimental.

The VUnit project mission is to apply best SW testing practises to the world of HDLs by providing the tools missing to adapt to such practises. The major missing piece is the unit testing framework, hence the name V(HDL)Unit. However, VUnit also provides supporting functionality not normally considered as a part of an unit testing framework.

• Builds on the commonly used xUnit architecture.
• Python test runner that enables powerful test administration, can handle fatal run-time errors (e.g. division by zero), and ensures test case independence.
• Scanners for identifying files, tests, file dependencies, and file changes enable automatic (re)compilation and execution of test suites.
• Can run test cases in parallel to take advantage of multi-core machines.
• Scriptable API as well as command line support.
• Support for running same test suite with different generics.
• VHDL test runner which enables test execution for not fully supported simulators.
• Assertion checker library that extends VHDL built-in support (assert).
• Logging framework supporting display and file output, different log levels, filtering on level and design hierarchy, output formatting and multiple loggers. Spreadsheet tool integration.
• Location preprocessor that traces log and check calls back to file and line number.
• JUnit report files for better Jenkins integration.

VUnit depends on a number of components as listed below. Full VUnit functionality requires Python and a simulator supported by the VUnit Python test runner. However, VUnit can run with limited functionality entirely within VHDL which means that unsupported simulators can be used as well. Prototype work has been done to fully support other simulators but this work is yet to be completed and released.

• VHDL-93
• VHDL-2002
• VHDL-2008
• Verilog
• SystemVerilog

• Windows
• Linux
• Mac OS X

• Python 2.7
• Python 3.3 or higher

• Tested with Riviera-PRO 2015.06, 2015.10, 2016.02 (x64/x86).
• Only VHDL

• Tested with Active-HDL 9.3, 10.1, 10.2, 10.3 (x64/x86)
• Only VHDL

• Tested with 10.1 - 10.4

• Only VHDL
• Works with versions >= 0.33
• Tested with LLVM and mcode backends, gcc backend might work aswell.
• Integrated support for using GTKWave to view waveforms.

The starting point for everything is http://vunit.github.io