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opensource:uvvm:start [21.09.2016 16:47]
espen.tallaksen
opensource:uvvm:start [19.01.2017 13:42]
espen.tallaksen [Scope]
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 UVVM is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches. UVVM is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches.
  
-Overview, Readability,​ Maintainability,​ Extensibility and Reuse are all vital for FPGA development efficiency and quality. UVVM VVC (VHDL Verification Component) Framework was released in 2016 as a  to handle exactly these aspects.+Overview, Readability,​ Maintainability,​ Extensibility and Reuse are all vital for FPGA development efficiency and quality. UVVM VVC (VHDL Verification Component) Framework was released in 2016 as a general solution ​to handle exactly these aspects.
  
 UVVM is a verification component system that allows the implementation of a very structured testbench architecture to handle medium complexity verification challenges and upwards. A key benefit of this system is the very simple software-like VHDL test sequencer that may control your complete testbench architecture with any number of verification components. This takes overview, readability and maintainability to a new level. UVVM is a verification component system that allows the implementation of a very structured testbench architecture to handle medium complexity verification challenges and upwards. A key benefit of this system is the very simple software-like VHDL test sequencer that may control your complete testbench architecture with any number of verification components. This takes overview, readability and maintainability to a new level.
opensource/uvvm/start.txt · Last modified: 09.02.2017 11:45 by espen.tallaksen