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Universal VHDL Verification Methodology (UVVM)

License The MIT License (MIT)
Tags VHDL, verification, testbench, simulation, VVC, Verification Component, Infrastructure, Architecture


UVVM is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches.

Overview, Readability, Maintainability, Extensibility and Reuse are all vital for FPGA development efficiency and quality. UVVM VVC (VHDL Verification Component) Framework was released in 2016 as a general solution to handle exactly these aspects.

UVVM is a verification component system that allows the implementation of a very structured testbench architecture to handle medium complexity verification challenges and upwards. A key benefit of this system is the very simple software-like VHDL test sequencer that may control your complete testbench architecture with any number of verification components. This takes overview, readability and maintainability to a new level.

Main Features

  • Very usefull support for checking values, ranges, time aspects, and for waiting for events inside a given window
  • An extremely low user threshold for the basic functionality - like logging, alert handling and checkers
  • A very structured testbench architecture that allows LEGO-like testbench/harness implementation
  • A very structured VHDL Verification Component (VVC) architecture that allows simultaneous activitity (stimuli and checking) on multiple interfaces in a very easily understandable manner
  • An easily understandable command syntax to control a complete testbench with multiple VVCs
  • The structure and overview is easily kept even for a testbench with a large number of VVCs
  • A VVC architecture that is almost exactly the same from one VVC to another - sometimes with only the BFM calls as the differentiator, thus allowing an extremely efficient reuse from one VVC to another
  • A VVC architecture that easily allows multiple threads for e.g. simultaneous Avalon Command and Response
  • A VVC architecture that allows simple encapsulation for ALL verification functionality for any given interface or protocol
  • Allows VVCs to be included anywhere in the test harness - or even inside the Design it self
  • A logging and alert system that supports full verbosity control of functionality and hierarchy
  • A logging system that lets you easily see how your commands propagate from your central test sequencer to your VVCs - through the execution queue - until it is executed and completed towards the DUT
  • Allows OSVVM randomisation and functional coverage to be included in the central test sequencer - or even better - inside the VVCs in the local sequencers for better control and encapsulation
  • Simple integration with regression test tools like Jenkins
  • Quick references are available for UVVM Utility Library, VVC System and all the BFMs/VVCs

Available VVCs and BFMs (Bus Functional Models)

These VVCs and BFMs could be used inside a typical UVVM testbench, but they could also be used stand-alone - e.g. as a BFM or VVC to handle just the AXI4-Lite interface with everything else being your proprietary testbench and methodology.

  • AXI4-Lite
  • AXI-Stream
  • Avalon MM
  • SBI (Simple Bus Interface - A single cycle simple parallel bus interface)
  • UART
  • SPI
  • I2C
  • More are coming


  • VHDL-2008
  • VHDL-2002 and VHDL-93 is only possible with the previous generation 'Bitvis Utility Library'

Supported Simulators

  • Aldec Active-HDL
  • Aldec Riviera Pro
  • Mentor Graphics Modelsim
  • Mentor Graphics Questa
  • Vivado: Awaiting proper VHDL 2008 support
  • GHDL: Awaiting test using compiled GHDL (Reported GHDL bug is said to have been fixed)

Getting Started

  • An extremely simple start could be to run UVVM Utility Library first.
    • Start by browsing through the PowerPoints under UVVM_Utility_Library/uvvm_util or watch the webinar linked from our web site
    • A demo is available under UVVM_Utility_Library/uvvm_util
  • To start with the VVC framework it is recommended to read the simple introduction to the system given under
  • A demo is available to see how UVVM works in a small testbench
opensource/uvvm/start.txt · Last modified: 09.02.2017 11:45 by espen.tallaksen