|License||The MIT License (MIT)|
|Tags||VHDL, verification, testbench, simulation, VVC, Verification Component, Infrastructure, Architecture|
UVVM is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches.
Overview, Readability, Maintainability, Extensibility and Reuse are all vital for FPGA development efficiency and quality. UVVM VVC (VHDL Verification Component) Framework was released in 2016 as a general solution to handle exactly these aspects.
UVVM is a verification component system that allows the implementation of a very structured testbench architecture to handle medium complexity verification challenges and upwards. A key benefit of this system is the very simple software-like VHDL test sequencer that may control your complete testbench architecture with any number of verification components. This takes overview, readability and maintainability to a new level.
These VVCs and BFMs could be used inside a typical UVVM testbench, but they could also be used stand-alone - e.g. as a BFM or VVC to handle just the AXI4-Lite interface with everything else being your proprietary testbench and methodology.