User Tools

Site Tools


Sidebar

GitHub

CoreLib

Sponsors

This website is sponsored by

Notes

This wiki uses icons from icons8.com licensed under CC BY-ND 3.0.

opensource:poc:start

Pile of Cores (PoC)

NamePoC
LicenseApache License 2.0
Repositoryhttps://github.com/VLSI-EDA/PoC
Documentationhttp://poc-library.readthedocs.io/
Contact https://gitter.im/VLSI-EDA/PoC
TagsIP Cores, Packages, Testbenches, Constraint Files, Python Infrastructure, Simulation, Synthesis

PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.

All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a better hierarchy.

Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based Infrastructure to offer a command line based frontend.

opensource/poc/start.txt · Last modified: 31.08.2016 21:43 by paebbels