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This wiki uses icons from icons8.com licensed under CC BY-ND 3.0.
Name | OSVVM |
---|---|
License | Artistic 3.0 |
Repository | https://github.com/JimLewis/OSVVM |
Documentation | https://github.com/JimLewis/OSVVM/tree/master/doc |
Tags | simulation, testbench, coverage, randomization |
Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology that simplifies implementation of functional coverage, constrained random, Intelligent Coverage Randomization, transcripting, Alerts and Logs, Memory Models, and Scoreboards.
OSVVM is implemented as a library of free, open-source packages. OSVVM uses these packages to create a features that rival language based implementations in both conciseness, simplicity, and capability. In particular, OSVVM uses these packages to create an Intelligent Coverage verification methodology that is a step ahead of other verification methodologies, such as SystemVerilog’s UVM.