Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology that simplifies implementation of functional coverage, constrained random, Intelligent Coverage Randomization, transcripting, Alerts and Logs, Memory Models, and Scoreboards.

OSVVM is implemented as a library of free, open-source packages. OSVVM uses these packages to create a features that rival language based implementations in both conciseness, simplicity, and capability. In particular, OSVVM uses these packages to create an Intelligent Coverage verification methodology that is a step ahead of other verification methodologies, such as SystemVerilog’s UVM.