A LGPL3 licensed library of reusable components for VHDL designs and testbenches.

The intention of this library is not to realize the most optimized and highest performing code. Instead it serves more as an example how to implement various things in VHDL and test them efficiently.

It contains for example:

• SPI Master/Slave simulation model
• Various implementations of queue (protected) types
• Implementation of dictionary (aka associative array) (protected) type
• Implementation of stack (protected) type
• SPI master/slave synthesizable RTL components
• Wishbone classic master/slave synthesizable RTL components
• Utils package with various helper functions (parity, countones …)
• Unit tests for all components