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opensource:fusesoc:start [31.08.2016 21:02]
olofk created
opensource:fusesoc:start [31.08.2016 21:41] (current)
paebbels
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 +====== FuseSoC ======
 +
 +^Name|FuseSoC|
 +^License| |
 +^Repository| https://​github.com/​olofk/​fusesoc ​ |
 +^Documentation| ​ |
 +^Tags| ​ |
 +
 [[https://​github.com/​olofk/​fusesoc|FuseSoC]] is a package manager and a set of build tools for HDL (Hardware Description Language) code. [[https://​github.com/​olofk/​fusesoc|FuseSoC]] is a package manager and a set of build tools for HDL (Hardware Description Language) code.
  
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 A collection of cores together with a top-level is called a system, and systems can be simulated or passed through the FPGA vendor tools to build a loadable FPGA image. A collection of cores together with a top-level is called a system, and systems can be simulated or passed through the FPGA vendor tools to build a loadable FPGA image.
  
-Currently FuseSoc supports simulations with ModelSim, Icarus Verilog, Verilator, Isim and Xsim. It also supports building FPGA images with Xilinx ISE and Altera Quartus+Currently FuseSoc supports simulations with ModelSim, Icarus Verilog, Verilator, Isim and Xsim. It also supports building FPGA images with Xilinx ISE and Altera Quartus.
opensource/fusesoc/start.1472677322.txt.gz · Last modified: 31.08.2016 21:02 by olofk